This invention relates setting a speed of clocked circuitry.
When laying out a computer design, and in accordance with at least one industry standard specification (PCI Local Bus Specification Rev. 2.2 published by the PCI Special Interest Group) the computer main (primary) bus over which a central processing unit (CPU) communicates with memory is frequently electronically isolated from other devices which may also from time to time wish to communicate with the CPU or memory. This isolation offers advantages such as the increased bus speed resulting from decreased parasitic capacitance, and allowing slower devices to communicate with the primary bus while not requiring that the primary bus be permanently slowed down to the speed of the slowest device (agent) on the bus.
A class of devices called bridges provides electrical isolation of a computer main bus from one or more secondary buses controlled by one or more bridges. A bridge participates in managing communication between a secondary bus and the main or primary computer bus. The bridge, in cooperation with the CPU, controls the sequencing of operations and access to the primary bus in accordance with the bus specification. An agent on a secondary bus requesting to communicate with another agent (which could either be on the same secondary bus, another secondary bus or on the primary bus) communicates this fact to the bridge controlling the secondary bus on which the requesting agent is attached. The agent asserts one or more signals requesting permission to send or receive over the primary bus. The bridge communicates with the CPU and upon receipt of the necessary acknowledgment and permission signals, allows the requesting device to access resources that reside on or beyond the primary bus through the bridge. In effect, the bridge operates as a traffic cop between the primary bus and the secondary bus. It is not necessary that the operating frequency of the secondary bus be the same as the operating frequency of the primary bus. A bus bridge typically takes care of providing any necessary synchronization between the two bus clocking domains.
Frequently, the secondary bus provides one or more slots into which circuit cards (agents) may be inserted by a user. In an open access computer system such as a personal computer with user accessible I/O expansion slots, it is generally not known at the time a particular circuit board is designed what specific peripheral cards may be inserted into the expansion slots. Circuit cards may be changed by users from time to time. Different cards may have different speed capabilities. For example, one card may have a maximum operating frequency of 66 MHz, while another card may have a maximum operating frequency of 133 MHz.) Current industry bus architecture specifications often provide a means of detecting the maximum operating speed capabilities of agents inserted into slots on the secondary bus. While this is necessary information, it is not sufficient to correctly establish the proper maximum operating frequency of the bus.
The physical loading of the secondary bus, primarily dependent upon the number of slots on a secondary bus as well as other design layout considerations, has an effect on the maximum operating frequency at which the secondary bus may operate. The greater the number of slots, generally, the lower the maximum speed at which the secondary bus is capable of operating. Simply configuring a secondary bus to be clocked at a fixed frequency equal to the maximum speed based upon physical loading alone does not take into account agents which may be inserted into slots on the secondary bus. One or more such agents may be slower than the fixed established secondary bus operating frequency, and accordingly, such agents may not operate correctly on the secondary bus under such circumstances.
For example, a two slot secondary bus may be capable of operating at speeds up to 66 MHz. Hard wiring the bus speed to 66 MHz means that slower devices, such as agents capable of operating no faster than 33 MHz, will not operate correctly. A faster card, one that is capable of running at 133 MHz, should be able to be run at the slower speed.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features and advantages of the invention will become apparent from the description, the drawings, and the claims.